Static random access memory (SRAM) and dynamic random access memory (DRAM) are two examples of random access memory used to store digital data. DRAM cells have one transistor and one capacitor, which stores a single bit of data based on the charge of the capacitor. Since the charge of a capacitor will diminish over time, continuous refreshing of the charge on the capacitor is required to retain the data bit. However, SRAM cells have multiple transistors and do not require continuous refreshing of the charge, allowing for storage of a data bit indefinitely as long as power is supplied.
An embodiment of a six transistor SRAM cell comprises four transistors that form two cross-coupled inverters and two pass-gate transistors, connecting the inverters to a first bitline and a second bitline. The two pass-gate transistors are controlled by a wordline that operates the read or write functions of the SRAM. In a read operation, the pass-gate transistors are switched on after the bitlines are precharged and allowed to float, allowing the state retained at storage nodes of the cross coupled inverters to be transferred to the bitlines. In a write operation, the pass-gate transistors are switched on, and the voltage on the bitline or the complementary bitline is raised to a certain level to alter the memory state of the cell.
The six transistor SRAM cell is known to suffer from a lack of stability and writeability. The stability issue occurs when a current through the pass-gate increases a bias on the internal node above the switching point of the inverter, causing the SRAM cell to switch states. The writeability issue occurs when a current discharge through the pass-gate fails to lower the bias on the internal node, preventing the cell from being written.
Optimization and targeting of the SRAM cell may be used to optimize between writeability and stability. But in specific applications, device targeting is not sufficient for both the read and write requirements. In these applications two additional transistors can be added to the six transistor SRAM cell to create a separate read port. This allows for a SRAM cell to be read from without discharging the internal nodes, which avoids the stability issues described above. While this improves the read operation, all SRAM cells along a particular wordline must be written simultaneously. This requires additional power that could be conserved if all cells along the wordline did not need to be written.
Considering the foregoing, it would be desirable to provide a memory array that allows an individual SRAM cell to be written without requiring all SRAM cells along a wordline to be written. This permits optimization of power usage and array size. Furthermore, other desirable features and characteristics will become apparent from the following detailed description and the appended Claims taken in conjunction with the accompanying drawings and this Background.